CMOS弛豫振荡器50%功耗降低方案

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824051

Byungjoon Song, Hwi-Cheol Kim, Youngdon Choi, Wonchan Kim

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引用次数: 27

摘要

本文设计了一种CMOS弛豫振荡器。与发射极耦合多振子不同，所提出的振荡器只有一个尾电流源。尾电流全部流经定时电容，从而使定时电容的充电斜率加倍。这在不增加功耗的情况下提高了运行速度。该振荡器采用标准的0.8 /spl mu/m CMOS工艺制造。在3.3 V单电源下，最大工作频率为923 MHz，而振荡器的电压为6 mA。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 50% power reduction scheme for CMOS relaxation oscillator

In this paper, a CMOS relaxation oscillator is presented. The proposed oscillator has only one tail current source unlike the emitter coupled multivibrator. All the tail current flows through the timing capacitor and thus the charging slope of the timing capacitor is doubled. This enhances the operating speed without increasing the power consumption. The oscillator is fabricated in a standard 0.8 /spl mu/m CMOS process. The maximum operating frequency is 923 MHz at a 3.3 V single supply, while the oscillator draws 6 mA.

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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