{"title":"降低数字方阵定时恢复的系统复杂度","authors":"K. Schmidt, A. Wittneben","doi":"10.1109/VETEC.1992.245421","DOIUrl":null,"url":null,"abstract":"A systematic approach to the complexity minimization of digital square timing recovery is discussed. It is demonstrated that, for narrowband data signals, a prefilter is mandatory to suppress the pattern noise. A least squared error approach is used to determine the tap weights of an FIR prefilter implementation. The data interpolator coefficients are optimized using a minimum mean squared error method. Two versions of the clock recovery are considered. One is based on a processing rate of two samples per symbol for the prefilter and data interpolator. The squarer and postprocessor (time extractor) part require four samples/symbol. A prefilter interpolator is used for upsampling. The other version processes four samples per symbol in all blocks. A postprocessing method is proposed, which reduces the complexity of the postprocessor block by 25% in comparison with the DFT-approach. Depending on the excess bandwidth factor r of the data signal, 15-21 multiply and accumulate operations per symbol are sufficient for a blockwise timing estimation.<<ETX>>","PeriodicalId":114705,"journal":{"name":"[1992 Proceedings] Vehicular Technology Society 42nd VTS Conference - Frontiers of Technology","volume":"61 1-4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Systematic complexity reduction for digital square timing recovery\",\"authors\":\"K. Schmidt, A. Wittneben\",\"doi\":\"10.1109/VETEC.1992.245421\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A systematic approach to the complexity minimization of digital square timing recovery is discussed. It is demonstrated that, for narrowband data signals, a prefilter is mandatory to suppress the pattern noise. A least squared error approach is used to determine the tap weights of an FIR prefilter implementation. The data interpolator coefficients are optimized using a minimum mean squared error method. Two versions of the clock recovery are considered. One is based on a processing rate of two samples per symbol for the prefilter and data interpolator. The squarer and postprocessor (time extractor) part require four samples/symbol. A prefilter interpolator is used for upsampling. The other version processes four samples per symbol in all blocks. A postprocessing method is proposed, which reduces the complexity of the postprocessor block by 25% in comparison with the DFT-approach. Depending on the excess bandwidth factor r of the data signal, 15-21 multiply and accumulate operations per symbol are sufficient for a blockwise timing estimation.<<ETX>>\",\"PeriodicalId\":114705,\"journal\":{\"name\":\"[1992 Proceedings] Vehicular Technology Society 42nd VTS Conference - Frontiers of Technology\",\"volume\":\"61 1-4\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-05-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1992 Proceedings] Vehicular Technology Society 42nd VTS Conference - Frontiers of Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VETEC.1992.245421\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1992 Proceedings] Vehicular Technology Society 42nd VTS Conference - Frontiers of Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VETEC.1992.245421","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Systematic complexity reduction for digital square timing recovery
A systematic approach to the complexity minimization of digital square timing recovery is discussed. It is demonstrated that, for narrowband data signals, a prefilter is mandatory to suppress the pattern noise. A least squared error approach is used to determine the tap weights of an FIR prefilter implementation. The data interpolator coefficients are optimized using a minimum mean squared error method. Two versions of the clock recovery are considered. One is based on a processing rate of two samples per symbol for the prefilter and data interpolator. The squarer and postprocessor (time extractor) part require four samples/symbol. A prefilter interpolator is used for upsampling. The other version processes four samples per symbol in all blocks. A postprocessing method is proposed, which reduces the complexity of the postprocessor block by 25% in comparison with the DFT-approach. Depending on the excess bandwidth factor r of the data signal, 15-21 multiply and accumulate operations per symbol are sufficient for a blockwise timing estimation.<>