{"title":"基于0.13 μm标准数字CMOS技术的运算放大器1/f降噪架构","authors":"J. Koh, Jungeun Lee, Chun-Deok Suh, Hoon-Tae Kim","doi":"10.1109/ASSCC.2006.357880","DOIUrl":null,"url":null,"abstract":"We present new circuit architecture for the 1/f noise reduction in a CMOS Miller operational amplifier. Compared to a reference circuit, the 1/f noise reduction of 7 dB is achieved for a CMOS Miller operational amplifier implemented in a 0.13 μm 1.5 V standard CMOS technology. This architecture successfully reduces the 1/f noise and is applicable to a continuous signal processing analog IC's.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"26 7","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 1/f-Noise Reduction Architecture for an Operational Amplifier in a 0.13 μm Standard digital CMOS technology\",\"authors\":\"J. Koh, Jungeun Lee, Chun-Deok Suh, Hoon-Tae Kim\",\"doi\":\"10.1109/ASSCC.2006.357880\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present new circuit architecture for the 1/f noise reduction in a CMOS Miller operational amplifier. Compared to a reference circuit, the 1/f noise reduction of 7 dB is achieved for a CMOS Miller operational amplifier implemented in a 0.13 μm 1.5 V standard CMOS technology. This architecture successfully reduces the 1/f noise and is applicable to a continuous signal processing analog IC's.\",\"PeriodicalId\":142478,\"journal\":{\"name\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"26 7\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2006.357880\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1/f-Noise Reduction Architecture for an Operational Amplifier in a 0.13 μm Standard digital CMOS technology
We present new circuit architecture for the 1/f noise reduction in a CMOS Miller operational amplifier. Compared to a reference circuit, the 1/f noise reduction of 7 dB is achieved for a CMOS Miller operational amplifier implemented in a 0.13 μm 1.5 V standard CMOS technology. This architecture successfully reduces the 1/f noise and is applicable to a continuous signal processing analog IC's.
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