Comparison of branch prediction schemes for superscalar processors ICEEC 2004

Instruction-level parallelism (ILP) in superscalar architectures makes use of deep pipelines in order to execute multiple instructions per cycle. The fvequency and behavior of branch instructions seriously affect performance of ILP processors. Various mechanisms, both at the compiler, as well as the processor level, have been proposed to predict the branch behavior. In this work, we have investigated various branch predictors at processor level to do a fair comparison among them. A practical implementation is described using several SPECintOO and SPECfpOO benchmarks and similar key parameters for evaluating these predictors. The branch-prediction schemes chosen for these comparisons are statically tokenhot-taken, bimodal, Combination, correlation, twolevel adaptive, hybrid, and gshare branch predictors. The results show that predictors which do not use global history registers, or which hash the global history register with the branch address or other values will bene$t fvom the predictor table interference reduction and increasing the table lengths. Two-level, gshare, and hybrid are the most promising predictor schemes available.