基于电压对比测试结构的快速在线过程窗口表征用于先进FinFET技术的发展

Weihong Gao, JeongHee Kim, Hsiao-Chi Peng, C. Huang, O. Patterson, yu-chi Su, Hsiang-Ting Yeh, Sean Starr-baier, Haokun Hu
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引用次数: 4

摘要

描述了一种使用电压对比(VC)测试结构家族的快速过程窗口表征方法。虽然VC测试结构已经在半导体行业的目标应用中普遍使用了二十年,但我们建议将VC测试结构作为大大加速半导体技术发展的强大工具进行全面应用。可以开发测试芯片,基本上涵盖所有可能的故障机制。这些芯片包括用于监控关键过程窗口和名义故障率的结构系列。这些结构被在线检测,从而为分裂实验评估、产量投影和偏移检测提供最早的反馈。本文报道了该方法在先进的FinFET技术中的应用。描述了测试结构布局、检查设置、分组策略和报告的最佳方法。给出了一些试验结构的设计和结果来说明这些原理。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Rapid In-line Process Window Characterization Using Voltage Contrast Test Structures for Advanced FinFET Technology Development
A methodology for rapid process window characterization using families of voltage contrast (VC) test structures is described. While VC test structures have been in common use in the semiconductor industry for targeted applications for twenty years, we propose comprehensive application of VC test structures as a powerful tool for greatly accelerating semiconductor technology development. Test chips may be developed covering essentially all possible failure mechanisms. These chips include families of structures for monitoring both the critical process windows and the nominal failure rate. These structures are inspected in-line thereby providing the earliest possible feedback for split experiment evaluation, yield projection, and excursion detection. This paper reports on the application of this methodology to an advanced FinFET technology. Best methods for test structure layout, inspection setup, and binning strategy and reporting are described. Selected test structure designs and results are presented to illustrate these principles.
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