晶圆在500 nm以下减薄时锁存灵敏度的TCAD研究

2021 International Semiconductor Conference (CAS) Pub Date : 2021-10-06 DOI:10.1109/CAS52836.2021.9604133

G. Hiblot, K. Serbulova, G. Hellings, Shih-Hung Chen

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引用次数: 1

摘要

利用TCAD仿真研究了锁存效应对晶圆厚度的敏感性。首先评估双极电阻和阱电阻对衬底厚度的依赖性，然后用于评估锁存电路的环路增益。最后采用瞬态模拟来评估锁存弹性作为衬底厚度的函数。

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TCAD study of latch-up sensitivity to wafer thinning below 500 nm

The sensitivity of latch-up to wafer thickness is investigated with TCAD simulations. The dependency of bipolar and well resistances on substrate thickness is first evaluated, and later used to assess the loop gain of the latch-up circuit. Transient simulations are finally employed to assess the latch-up resilience as a function of substrate thickness.

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2021 International Semiconductor Conference (CAS)

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