Yasser Moursy, T. Rosa, Lionel Jure, A. Quelen, S. Genevey, L. Pierrefeu, E. Collins, Joerg Winkler, Jonathan Park, G. Pillonnet, V. Huard, A. Bonzo, P. Flatresse
{"title":"采用22nm FDSOI技术的0.021mm2 pvt感知数字流兼容自适应背偏调节器,具有可扩展驱动器,实现450%的频率提升和30%的功耗降低","authors":"Yasser Moursy, T. Rosa, Lionel Jure, A. Quelen, S. Genevey, L. Pierrefeu, E. Collins, Joerg Winkler, Jonathan Park, G. Pillonnet, V. Huard, A. Bonzo, P. Flatresse","doi":"10.1109/ISSCC42613.2021.9365782","DOIUrl":null,"url":null,"abstract":"A near-threshold power supply aims to operate at the minimal energy point but suffers from high-sensitivity to process, temperature and voltage variations. Adaptive voltage scaling (AVS) is a well-known strategy to adapt the power supply to die-to-die and temperature variations [1]. However, AVS needs dedicated power supplies with nonnegligible overheads, e.g. extra die area, lower power converter efficiency, and with granularity limitations or complex fine-grain integration in the power mesh. SOI-based technologies offer unique features by biasing the wells below the transistors to tune the threshold voltage ($\\mathrm{V}_{\\mathrm{T}\\mathrm{H}}$). The well-known adaptive back-biasing (ABB) technique has already shown its capability to reduce power consumption or/and maintain operating frequency by compensating $\\mathrm{V}_{\\mathrm{T}\\mathrm{H}}$ variability according to process corners and temperature [1–5]. However, previously published ABB architectures provide a limited overview on how to integrate the ABB seamlessly in the digital design flow with industrial-grade qualification. We propose a reusable ABB-IP for any biased digital load, from 0.4-100 mm2, with low area and power overhead, e.g. 1.2% @ 2mm2 and 0.4% @ 10mm2, respectively. We properly quantify the gain in a mass-production context with a large statistical scope analysis across 316 measured dies from different split-wafer lots and from -40 to 125°C with a representative load (a Cortex M4F). Thanks to 3V asymmetrical wells amplitude swing, our ABB-IP brings up to 30% power reduction by decreasing the minimal power supply byl00mV, while maintaining the target operating frequency (50 MHz) with a high yield. Distributed timing monitors (DTM) guarantee an accurate timing monitoring of the biased digital load, while scalable well drivers adjust to the biased well area, enabling the ABB-IP genericity.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"22 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology\",\"authors\":\"Yasser Moursy, T. Rosa, Lionel Jure, A. Quelen, S. Genevey, L. Pierrefeu, E. Collins, Joerg Winkler, Jonathan Park, G. Pillonnet, V. Huard, A. Bonzo, P. Flatresse\",\"doi\":\"10.1109/ISSCC42613.2021.9365782\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A near-threshold power supply aims to operate at the minimal energy point but suffers from high-sensitivity to process, temperature and voltage variations. Adaptive voltage scaling (AVS) is a well-known strategy to adapt the power supply to die-to-die and temperature variations [1]. However, AVS needs dedicated power supplies with nonnegligible overheads, e.g. extra die area, lower power converter efficiency, and with granularity limitations or complex fine-grain integration in the power mesh. SOI-based technologies offer unique features by biasing the wells below the transistors to tune the threshold voltage ($\\\\mathrm{V}_{\\\\mathrm{T}\\\\mathrm{H}}$). The well-known adaptive back-biasing (ABB) technique has already shown its capability to reduce power consumption or/and maintain operating frequency by compensating $\\\\mathrm{V}_{\\\\mathrm{T}\\\\mathrm{H}}$ variability according to process corners and temperature [1–5]. However, previously published ABB architectures provide a limited overview on how to integrate the ABB seamlessly in the digital design flow with industrial-grade qualification. We propose a reusable ABB-IP for any biased digital load, from 0.4-100 mm2, with low area and power overhead, e.g. 1.2% @ 2mm2 and 0.4% @ 10mm2, respectively. We properly quantify the gain in a mass-production context with a large statistical scope analysis across 316 measured dies from different split-wafer lots and from -40 to 125°C with a representative load (a Cortex M4F). Thanks to 3V asymmetrical wells amplitude swing, our ABB-IP brings up to 30% power reduction by decreasing the minimal power supply byl00mV, while maintaining the target operating frequency (50 MHz) with a high yield. Distributed timing monitors (DTM) guarantee an accurate timing monitoring of the biased digital load, while scalable well drivers adjust to the biased well area, enabling the ABB-IP genericity.\",\"PeriodicalId\":371093,\"journal\":{\"name\":\"2021 IEEE International Solid- State Circuits Conference (ISSCC)\",\"volume\":\"22 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-02-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Solid- State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC42613.2021.9365782\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC42613.2021.9365782","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology
A near-threshold power supply aims to operate at the minimal energy point but suffers from high-sensitivity to process, temperature and voltage variations. Adaptive voltage scaling (AVS) is a well-known strategy to adapt the power supply to die-to-die and temperature variations [1]. However, AVS needs dedicated power supplies with nonnegligible overheads, e.g. extra die area, lower power converter efficiency, and with granularity limitations or complex fine-grain integration in the power mesh. SOI-based technologies offer unique features by biasing the wells below the transistors to tune the threshold voltage ($\mathrm{V}_{\mathrm{T}\mathrm{H}}$). The well-known adaptive back-biasing (ABB) technique has already shown its capability to reduce power consumption or/and maintain operating frequency by compensating $\mathrm{V}_{\mathrm{T}\mathrm{H}}$ variability according to process corners and temperature [1–5]. However, previously published ABB architectures provide a limited overview on how to integrate the ABB seamlessly in the digital design flow with industrial-grade qualification. We propose a reusable ABB-IP for any biased digital load, from 0.4-100 mm2, with low area and power overhead, e.g. 1.2% @ 2mm2 and 0.4% @ 10mm2, respectively. We properly quantify the gain in a mass-production context with a large statistical scope analysis across 316 measured dies from different split-wafer lots and from -40 to 125°C with a representative load (a Cortex M4F). Thanks to 3V asymmetrical wells amplitude swing, our ABB-IP brings up to 30% power reduction by decreasing the minimal power supply byl00mV, while maintaining the target operating frequency (50 MHz) with a high yield. Distributed timing monitors (DTM) guarantee an accurate timing monitoring of the biased digital load, while scalable well drivers adjust to the biased well area, enabling the ABB-IP genericity.