采用22nm FDSOI技术的0.021mm2 pvt感知数字流兼容自适应背偏调节器,具有可扩展驱动器,实现450%的频率提升和30%的功耗降低

Yasser Moursy, T. Rosa, Lionel Jure, A. Quelen, S. Genevey, L. Pierrefeu, E. Collins, Joerg Winkler, Jonathan Park, G. Pillonnet, V. Huard, A. Bonzo, P. Flatresse
{"title":"采用22nm FDSOI技术的0.021mm2 pvt感知数字流兼容自适应背偏调节器,具有可扩展驱动器,实现450%的频率提升和30%的功耗降低","authors":"Yasser Moursy, T. Rosa, Lionel Jure, A. Quelen, S. Genevey, L. Pierrefeu, E. Collins, Joerg Winkler, Jonathan Park, G. Pillonnet, V. Huard, A. Bonzo, P. Flatresse","doi":"10.1109/ISSCC42613.2021.9365782","DOIUrl":null,"url":null,"abstract":"A near-threshold power supply aims to operate at the minimal energy point but suffers from high-sensitivity to process, temperature and voltage variations. Adaptive voltage scaling (AVS) is a well-known strategy to adapt the power supply to die-to-die and temperature variations [1]. However, AVS needs dedicated power supplies with nonnegligible overheads, e.g. extra die area, lower power converter efficiency, and with granularity limitations or complex fine-grain integration in the power mesh. SOI-based technologies offer unique features by biasing the wells below the transistors to tune the threshold voltage ($\\mathrm{V}_{\\mathrm{T}\\mathrm{H}}$). The well-known adaptive back-biasing (ABB) technique has already shown its capability to reduce power consumption or/and maintain operating frequency by compensating $\\mathrm{V}_{\\mathrm{T}\\mathrm{H}}$ variability according to process corners and temperature [1–5]. However, previously published ABB architectures provide a limited overview on how to integrate the ABB seamlessly in the digital design flow with industrial-grade qualification. We propose a reusable ABB-IP for any biased digital load, from 0.4-100 mm2, with low area and power overhead, e.g. 1.2% @ 2mm2 and 0.4% @ 10mm2, respectively. We properly quantify the gain in a mass-production context with a large statistical scope analysis across 316 measured dies from different split-wafer lots and from -40 to 125°C with a representative load (a Cortex M4F). Thanks to 3V asymmetrical wells amplitude swing, our ABB-IP brings up to 30% power reduction by decreasing the minimal power supply byl00mV, while maintaining the target operating frequency (50 MHz) with a high yield. Distributed timing monitors (DTM) guarantee an accurate timing monitoring of the biased digital load, while scalable well drivers adjust to the biased well area, enabling the ABB-IP genericity.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"22 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology\",\"authors\":\"Yasser Moursy, T. Rosa, Lionel Jure, A. Quelen, S. Genevey, L. Pierrefeu, E. Collins, Joerg Winkler, Jonathan Park, G. Pillonnet, V. Huard, A. Bonzo, P. Flatresse\",\"doi\":\"10.1109/ISSCC42613.2021.9365782\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A near-threshold power supply aims to operate at the minimal energy point but suffers from high-sensitivity to process, temperature and voltage variations. Adaptive voltage scaling (AVS) is a well-known strategy to adapt the power supply to die-to-die and temperature variations [1]. However, AVS needs dedicated power supplies with nonnegligible overheads, e.g. extra die area, lower power converter efficiency, and with granularity limitations or complex fine-grain integration in the power mesh. SOI-based technologies offer unique features by biasing the wells below the transistors to tune the threshold voltage ($\\\\mathrm{V}_{\\\\mathrm{T}\\\\mathrm{H}}$). The well-known adaptive back-biasing (ABB) technique has already shown its capability to reduce power consumption or/and maintain operating frequency by compensating $\\\\mathrm{V}_{\\\\mathrm{T}\\\\mathrm{H}}$ variability according to process corners and temperature [1–5]. However, previously published ABB architectures provide a limited overview on how to integrate the ABB seamlessly in the digital design flow with industrial-grade qualification. We propose a reusable ABB-IP for any biased digital load, from 0.4-100 mm2, with low area and power overhead, e.g. 1.2% @ 2mm2 and 0.4% @ 10mm2, respectively. We properly quantify the gain in a mass-production context with a large statistical scope analysis across 316 measured dies from different split-wafer lots and from -40 to 125°C with a representative load (a Cortex M4F). Thanks to 3V asymmetrical wells amplitude swing, our ABB-IP brings up to 30% power reduction by decreasing the minimal power supply byl00mV, while maintaining the target operating frequency (50 MHz) with a high yield. Distributed timing monitors (DTM) guarantee an accurate timing monitoring of the biased digital load, while scalable well drivers adjust to the biased well area, enabling the ABB-IP genericity.\",\"PeriodicalId\":371093,\"journal\":{\"name\":\"2021 IEEE International Solid- State Circuits Conference (ISSCC)\",\"volume\":\"22 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-02-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Solid- State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC42613.2021.9365782\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC42613.2021.9365782","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

近阈值电源旨在以最小能量点运行,但对工艺、温度和电压变化具有高度敏感性。自适应电压缩放(AVS)是一种众所周知的策略,使电源适应模对模和温度变化[1]。然而,AVS需要具有不可忽略的开销的专用电源,例如额外的模具面积,较低的功率转换器效率,以及在电源网格中存在粒度限制或复杂的细粒度集成。基于soi的技术提供了独特的功能,通过偏置晶体管下方的井来调节阈值电压($\ mathm {V}_{\ mathm {T}\ mathm {H}}$)。众所周知的自适应反偏(ABB)技术已经显示出其通过根据工艺角和温度补偿$\ mathm {V}_{\ mathm {T}\ mathm {H}}$的可变性来降低功耗或/并保持工作频率的能力[1-5]。然而,以前发布的ABB架构提供了关于如何将ABB无缝集成到具有工业级资质的数字设计流程中的有限概述。我们提出了一种可重复使用的ABB-IP,适用于任何偏置数字负载,范围从0.4-100 mm2,面积和功率开销低,例如,分别为1.2% @ 2mm2和0.4% @ 10mm2。在大规模生产的背景下,我们对来自不同晶圆批次的316个测量芯片进行了大规模的统计范围分析,并在-40至125°C的代表性负载(Cortex M4F)下适当地量化了增益。得益于3V的不对称井幅摆动,我们的ABB-IP通过将最小电源降低l00mv,降低了30%的功率,同时保持了目标工作频率(50 MHz)和高产量。分布式定时监控器(DTM)保证了对偏置数字负载的准确定时监测,同时可扩展的井驱动器可根据偏置井面积进行调整,从而实现ABB-IP的通用性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology
A near-threshold power supply aims to operate at the minimal energy point but suffers from high-sensitivity to process, temperature and voltage variations. Adaptive voltage scaling (AVS) is a well-known strategy to adapt the power supply to die-to-die and temperature variations [1]. However, AVS needs dedicated power supplies with nonnegligible overheads, e.g. extra die area, lower power converter efficiency, and with granularity limitations or complex fine-grain integration in the power mesh. SOI-based technologies offer unique features by biasing the wells below the transistors to tune the threshold voltage ($\mathrm{V}_{\mathrm{T}\mathrm{H}}$). The well-known adaptive back-biasing (ABB) technique has already shown its capability to reduce power consumption or/and maintain operating frequency by compensating $\mathrm{V}_{\mathrm{T}\mathrm{H}}$ variability according to process corners and temperature [1–5]. However, previously published ABB architectures provide a limited overview on how to integrate the ABB seamlessly in the digital design flow with industrial-grade qualification. We propose a reusable ABB-IP for any biased digital load, from 0.4-100 mm2, with low area and power overhead, e.g. 1.2% @ 2mm2 and 0.4% @ 10mm2, respectively. We properly quantify the gain in a mass-production context with a large statistical scope analysis across 316 measured dies from different split-wafer lots and from -40 to 125°C with a representative load (a Cortex M4F). Thanks to 3V asymmetrical wells amplitude swing, our ABB-IP brings up to 30% power reduction by decreasing the minimal power supply byl00mV, while maintaining the target operating frequency (50 MHz) with a high yield. Distributed timing monitors (DTM) guarantee an accurate timing monitoring of the biased digital load, while scalable well drivers adjust to the biased well area, enabling the ABB-IP genericity.
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