定时香农电路:一种节能设计风格和合成工具

32nd Design Automation Conference Pub Date : 1900-01-01 DOI:10.1145/217474.217538

L. Lavagno, P. McGeer, A. Saldanha, A. Sangiovanni-Vincentelli

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引用次数: 54

摘要

提出了一种利用香农图合成低功耗组合逻辑电路的方法，使一个n输入，m输出的电路使用具有无界扇出的2输入门实现，每个输入向量有O(nm)跃迁。在有界扇出模型下，转换活度最多增加了n倍。此外，功耗与电路延迟无关。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool

A method of synthesizing low-power combinational logic circuits from Shannon Graphs is proposed such that an n input, m output circuit realization using 2-input gates with unbounded fanout has O(nm) transitions per input vector. Under a bounded fanout model, the transition activity is increased at most by a factor of n. Moreover, the power consumption is independent of circuit delays.

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32nd Design Automation Conference

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