基于JPEG2000的高速车载图像压缩的双核ASIC架构

Proceedings of 5th International Conference on Recent Advances in Space Technologies - RAST2011 Pub Date : 2011-06-09 DOI:10.1109/RAST.2011.5966880

N. Ismailoglu, K. Karakus, K. Kapucu, Ozan Yilmaz, Y. M. Mert, H. E. Kazak, R. Oktem

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引用次数: 4

摘要

我们提出了一种双核JPEG2000架构，旨在实时压缩高分辨率多通道图像。提出的结构可以处理JPEG2000的无损压缩和率失真优化的有损压缩方案。在Xilinx Virtex-5系列FPGA上实现并仿真了双核JPEG2000架构。仿真结果表明，在100MHz的时钟速率下，该架构的编码速率可达200Mbits。

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A dual-core ASIC architecture for high-speed on-board image compression with JPEG2000

We propose a dual core JPEG2000 architecture which aims to compress high resolution multichannel images in real time. The proposed architecture handles both lossless and Rate Distortion-Optimized lossy compression schemes of JPEG2000. The dual core JPEG2000 architecture is implemented and simulated on a Xilinx Virtex-5 Series FPGA. The simulation results show that the proposed architecture can encode up to 200Mbits at 100MHz clock speed.

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Proceedings of 5th International Conference on Recent Advances in Space Technologies - RAST2011

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