二维有限记忆滤波器的收缩阵列实现

[1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings Pub Date : 1991-05-09 DOI:10.1109/PACRIM.1991.160836

S. Foda, M. Elmasry, P. Agathoklis

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引用次数: 0

摘要

提出了一种实时递归二维有限记忆滤波器的收缩阵列实现方案。利用递归有限内存滤波器的二维状态空间模型，推导出实时实现的流水线阵列。该技术基于迭代的块处理。并行实现是具有规则通信结构的广播、计算和聚合(BCA)范式。加工元件(pe)简单，易于设计和验证，使设计具有成本效益

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Systolic array implementation of 2-D finite memory filters

A scheme of systolic array implementation for recursive two-dimensional finite memory filters in real time is presented. A 2D state space model for recursive finite memory filters is used to derive a pipelined array for real-time implementation. The technique is based on block processing via iteration. The parallel implementation is a broadcast, calculate, and aggregate (BCA) paradigm with a regular communication structure. The processing elements (PEs) are simple and easy to design and verify, which makes the design cost effective.<>

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[1991] IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Conference Proceedings

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