{"title":"12位2.4 GHz D/A上变频","authors":"V. Turunen, Tero Nieminen, M. Kosunen, K. Halonen","doi":"10.1109/ECCTD.2007.4529578","DOIUrl":null,"url":null,"abstract":"This paper describes the design and implementation of a upconverting D/A converter (DAC). Designed converter is capable of upconverting two 12-bit 60 MHz (in-phase and quadrature) signal bands around 2.4 GHz radio frequency. Upconversion is implemented by reorganizing switching scheme of a traditional current-steering D/A converter. Designed with 0.13 mum CMOS process, total area and estimated power consumption including DSP are 8.14 mm2 and 520 mW respectively.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"210 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"12-bit 2.4 GHz D/A upconverter\",\"authors\":\"V. Turunen, Tero Nieminen, M. Kosunen, K. Halonen\",\"doi\":\"10.1109/ECCTD.2007.4529578\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design and implementation of a upconverting D/A converter (DAC). Designed converter is capable of upconverting two 12-bit 60 MHz (in-phase and quadrature) signal bands around 2.4 GHz radio frequency. Upconversion is implemented by reorganizing switching scheme of a traditional current-steering D/A converter. Designed with 0.13 mum CMOS process, total area and estimated power consumption including DSP are 8.14 mm2 and 520 mW respectively.\",\"PeriodicalId\":445822,\"journal\":{\"name\":\"2007 18th European Conference on Circuit Theory and Design\",\"volume\":\"210 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 18th European Conference on Circuit Theory and Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECCTD.2007.4529578\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 18th European Conference on Circuit Theory and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2007.4529578","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
本文介绍了一种上变频数模转换器(DAC)的设计与实现。所设计的转换器能够在2.4 GHz无线电频率上下转换两个12位60 MHz(同相和正交)信号频段。上变频是通过对传统电流导向数模转换器的开关方案进行重组来实现的。采用0.13 μ m CMOS工艺设计，包括DSP在内的总面积和估计功耗分别为8.14 mm2和520 mW。
This paper describes the design and implementation of a upconverting D/A converter (DAC). Designed converter is capable of upconverting two 12-bit 60 MHz (in-phase and quadrature) signal bands around 2.4 GHz radio frequency. Upconversion is implemented by reorganizing switching scheme of a traditional current-steering D/A converter. Designed with 0.13 mum CMOS process, total area and estimated power consumption including DSP are 8.14 mm2 and 520 mW respectively.
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