A 14bit 10MSps low power pipelined ADC with 0.99pJ/step FOM

A 14bit 10MS/s pipelined ADC in 0.18um CMOS process is presented. The amplifier sharing, the SHA removing and scaling down techniques are used for low power. Employing the PCEA (passive capacitor error averaging) technique, the mismatch of the capacitance can effectively overcome. The prototype ADC was fabricated in a 3.3V CMOS process. With a 15.5 MHz input signal, the ADC achieves 82.3dB SFDR and 11.5bit ENOB at 10MS/s. With a 2.4 MHz input signal, the ADC achieves 83.9dB SFDR and 11.75bit ENOB at 10MS/s. The power consumption is 34.2mW at 2.8V supply including output drivers. The chip occupies 2.1*2.1mm2, including pads.