高频低压时钟发生器的设计考虑

Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI:10.1109/ICM.2004.1434602

H. Shamsi, O. Shoaei, Azadeh Zahabi, Y. Koolivand, R. Doost

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引用次数: 1

摘要

报道了一种用于时钟产生的低电压、1.2 V、4 GHz CMOS锁相环。该低压时钟发生器由一个环形振荡器作为VCO组成，工作范围为100 MHz至4 GHz，最大功耗为11 mW。采用带适当环路滤波器的电荷泵电路，为压控振荡器提供无纹波控制电压。该锁相环在0.13 /spl mu/m CMOS技术下的总功耗约为54 mW。

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Design considerations of a high frequency and low voltage clock generator

A low voltage, 1.2 V, 4 GHz CMOS phase lock loop for clock generation is reported. This low voltage clock generator consists of a ring oscillator as the VCO that works from 100 MHz to 4 GHz with a maximum power consumption of 11 mW. Employing a charge pump circuit with suitable loop filter, a ripple free control voltage is provided for VCO. The total power consumption of this PLL, simulated in a 0.13 /spl mu/m CMOS technology, is about 54 mW.

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Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.

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