低功耗数字锁相环，具有一周期频率锁相时间和大倍频系数，用于先进的电源管理

Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI:10.1109/ICECS.1996.584629

R. Fried, Z. Azmanov

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引用次数: 6

摘要

提出了一种低功耗数字锁相环(DPLL)，具有+/- 100ps的抖动和一个周期的频率锁相环。使用32,768 Hz的参考时钟，产生最高100mhz的时钟频率。DPLL专为芯片级和系统级的高级电源管理和性能增强而设计。

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Low-power digital PLL with one cycle frequency lock-in time and large frequency-multiplication factor for advanced power management

A low-power Digital PLL (DPLL) with +/-100 ps jitter and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a 32,768 Hz reference clock. The DPLL is especially designed for advanced power management and performance enhancement, both at a chip level and system level.

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Proceedings of Third International Conference on Electronics, Circuits, and Systems

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