{"title":"低反向转移电容VDMOS晶体管","authors":"T. Sakai, N. Murakami","doi":"10.1109/PESC.1988.18197","DOIUrl":null,"url":null,"abstract":"A VDMOS (vertical double-diffused metal-oxide semiconductor) transistor structure is proposed that reduces reverse transfer capacitance. The structure features an additional p-region formed at the surface of the n-epitaxial layer, using a poly-Si gate as a mask. Its measured reverse transfer capacitance is about 50% less than that of the conventional VDMOS, and the rise time reduced 50%. measured I/sub D/-V/sub DS/, drain-source breakdown, and switching characteristics are also presented.<<ETX>>","PeriodicalId":283605,"journal":{"name":"PESC '88 Record., 19th Annual IEEE Power Electronics Specialists Conference","volume":"2007 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Low reverse transfer capacitance VDMOS transistor\",\"authors\":\"T. Sakai, N. Murakami\",\"doi\":\"10.1109/PESC.1988.18197\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A VDMOS (vertical double-diffused metal-oxide semiconductor) transistor structure is proposed that reduces reverse transfer capacitance. The structure features an additional p-region formed at the surface of the n-epitaxial layer, using a poly-Si gate as a mask. Its measured reverse transfer capacitance is about 50% less than that of the conventional VDMOS, and the rise time reduced 50%. measured I/sub D/-V/sub DS/, drain-source breakdown, and switching characteristics are also presented.<<ETX>>\",\"PeriodicalId\":283605,\"journal\":{\"name\":\"PESC '88 Record., 19th Annual IEEE Power Electronics Specialists Conference\",\"volume\":\"2007 4\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-04-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"PESC '88 Record., 19th Annual IEEE Power Electronics Specialists Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PESC.1988.18197\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"PESC '88 Record., 19th Annual IEEE Power Electronics Specialists Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PESC.1988.18197","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A VDMOS (vertical double-diffused metal-oxide semiconductor) transistor structure is proposed that reduces reverse transfer capacitance. The structure features an additional p-region formed at the surface of the n-epitaxial layer, using a poly-Si gate as a mask. Its measured reverse transfer capacitance is about 50% less than that of the conventional VDMOS, and the rise time reduced 50%. measured I/sub D/-V/sub DS/, drain-source breakdown, and switching characteristics are also presented.<>
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
