{"title":"Gras: A general framework for combining automatic code generation and register allocation","authors":"Kelvin S. Bryant , Jon Mauney","doi":"10.1016/0096-0551(95)00004-N","DOIUrl":null,"url":null,"abstract":"<div><p>We present a system for producing retargetable code generators containing coloring-based register allocators. The compiler writer specifies the overall register characteristics of the target machine, as well as the specific register requirements of individual assembly instructions. A Code Generator Prepass processes the specific instruction requirements so that they can be considered during register allocation. We also present our notion of “generic” coloring algorithms which simplify the retargeting of register allocators to different architectures. The system is suitable for RISC and CISC architectures</p></div>","PeriodicalId":100315,"journal":{"name":"Computer Languages","volume":"21 2","pages":"Pages 101-112"},"PeriodicalIF":0.0000,"publicationDate":"1995-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0096-0551(95)00004-N","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Computer Languages","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/009605519500004N","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We present a system for producing retargetable code generators containing coloring-based register allocators. The compiler writer specifies the overall register characteristics of the target machine, as well as the specific register requirements of individual assembly instructions. A Code Generator Prepass processes the specific instruction requirements so that they can be considered during register allocation. We also present our notion of “generic” coloring algorithms which simplify the retargeting of register allocators to different architectures. The system is suitable for RISC and CISC architectures