Design and Implementation of Multilayer Perceptron with On-chip Learning in Virtex-E

Abstract

Due to advancements in technology, many integrated circuits are fabricated to develop an artificial system that could perform “intelligent” tasks similar to those performed by the human brain. Many of them use off-chip learning method either by analog hardware or massively by parallel computers. This proposed work is about a trainable neural chip using Field Programmable Gate Array (FPGA) as this helps in learning capability by exploiting the inherent parallelism of neural network. By this fast prototyping is possible for real-time applications, such as speech recognition, speech synthesis, image processing, pattern recognition and classification. In this work on-chip learning method is designed for standard benchmark XOR problem using back propagation based multilayer perceptron and is implemented in VIRTEX-E FPGA using VHDL. The design works at 5.332 MHz and the total gate count is 4, 73,237.