Transistor Sizing using Hybrid Reinforcement Learning and Graph Convolution Neural Network Algorithm

Abstract

Transistor sizing is one the developing field in VLSI. Many researches have been conducted to achieve automatic transistor sizing which is a complex task due to its large design area and communication gap between different node and topology. In this paper, automatic transistor sizing is implemented using a combinational methods of Graph Convolutional Neural Network (GCN) and Reinforcement Learning (RL). In the graphical structure the transistor are represented as apexes and the wires are represented as boundaries. Reinforcement learning techniques acts a communication bridge between every node and topology of all circuit. This brings proper communication and understanding among the circuit design. Thus the Figure of Merit (FOM) is increased and the experimental results are compared with different topologies. It is proved that the circuit with prior knowledge about the system, performs well.