High-performance reverse converter design for the new four-moduli Set {22n, 2n+1, 2n/2+1, 2n/2-1}

Abstract

This paper presents a new four-moduli set {2²ⁿ, 2ⁿ +1, 2^n/2+1, 2^n/2-1} (where n is an even number) for meeting scale criteria. According to the new Chinese reminder theorem 1, the proposed moduli set can derive an efficient reverse conversion algorithm, and the converter architecture can then be designed. The proposed converter with a 32-bit width was implemented using the TSMC 90-nm complementary metal-oxide semiconductor process. The chip area is 980 × 920 μm² and the working frequency is 133 MHz. Savings of delay and power performance of more than 26.9% and 18.4%, respectively, are achieved using the proposed design.