A 4 channel analog front end for central office ADSL modems

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852673

J. Kenney, Faramarz Sabouri, V. Leung, J. Guido, E. Zimany, A. Agrillo, J. Trackim, J. Khoury, Reza Shariatdous

引用次数: 5

Abstract

This chip integrates a 4 channel analog front-end for central office ADSL modems. The receive path has a programmable gain amplifier (PGA) with 30 dB of range followed by a fourth-order 2-bit sigma-delta modulator clocking at 35 MHz. The transmit path uses a 14-bit current steering D/A converter followed by a fourth-order low-pass filter. The device is implemented in 0.35 /spl mu/m CMOS and consumes less than 160 mW per channel. It is packaged in a 100 pin MQFP package.

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一个4通道模拟前端局ADSL调制解调器

该芯片集成了一个4通道模拟前端的中央局ADSL调制解调器。接收路径具有一个可编程增益放大器(PGA)，其范围为30db，随后是一个时钟频率为35mhz的四阶2位sigma-delta调制器。传输路径使用一个14位电流导向的D/ a转换器，然后是一个四阶低通滤波器。该器件以0.35 /spl mu/m CMOS实现，每个通道消耗低于160 mW。它被封装在一个100引脚的MQFP封装中。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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