A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB

Abstract

This paper presents a fractional-N PLL working in sub-sampling mode using a pipelined phase-interpolator. The proposed pipelined phase-interpolator can achieve high phase linearity with very low power consumption. The fractional-N sub-sampling PLL is implemented in a standard 65nm CMOS technology. The PLL works at a frequency ranging from 4.3GHz to 4.9GHz while consuming 3.3mW. The measured in-band phase noise in fractional-N mode is -114dBc/Hz at 400kHz offset from the carrier, while working with a bandwidth of approximately 2MHz. The combination of high-precision low-power phase-interpolation technique and the sub-sampling technique realizes a high-performance fractional-N frequency synthesizer with the highest reported FoM.