Novel VLIW code compaction method for a 3D geometry processor

H. Suzuki, H. Making, Y. Matsuda
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引用次数: 5

Abstract

A VLIW (very long instruction word) architecture with a new code compaction method has been proposed. For a 3D-geometry processor, we consider two types of 2-issue VLIW architectures, the floating-point execution accelerating VLIW (FP-VLIW) and the data-move enhancing VLIW (MV-VLIW) architectures, as expansions of a single SIMD (single instruction, multiple data) architecture. To solve the code bloat problem in common with VLIW architectures, the proposed method enables one to compact original codes into the VLIW codes by software tools and decompact the VLIW codes by a simple hardware decompactor composed of an instruction swap circuit on a chip. Speeds and code densities of the two VLIWs with the compaction method are compared to a reference processor with the same instruction set and the same building blocks. The speed of the FP-VLIW is the fastest in all test cases. It is 26%-30% faster than the reference processor. The proposed compaction method keeps the 94% code density of the reference processor. The FP-VLIW architecture with the code compaction achieves 1.2-1.3 times of the speed performance without significant code-density deterioration.
一种新颖的三维几何处理器VLIW代码压缩方法
提出了一种具有新的代码压缩方法的超长指令字(VLIW)体系结构。对于3d几何处理器,我们考虑了两种类型的2-issue VLIW架构,浮点执行加速VLIW (FP-VLIW)和数据移动增强VLIW (MV-VLIW)架构,作为单个SIMD(单指令,多数据)架构的扩展。为了解决VLIW体系结构中常见的代码膨胀问题,本文提出的方法可以通过软件工具将原始代码压缩成VLIW代码,并通过芯片上的指令交换电路组成的简单硬件反解码器对VLIW代码进行解压缩。将采用压缩方法的两个VLIWs的速度和代码密度与具有相同指令集和相同构建块的参考处理器进行比较。FP-VLIW的速度是所有测试用例中最快的。它比参考处理器快26%-30%。所提出的压缩方法保持了参考处理器94%的代码密度。具有代码压缩的FP-VLIW架构在没有显著代码密度下降的情况下实现了1.2-1.3倍的速度性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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