The potential of poly-Si nanowire FETs featuring independent double-gated configuration for nonvolatile memory applications

Abstract

A simple and low-cost approach is proposed to fabricate SONOS devices featuring poly-Si nanowire (NW) and independent double-gated (IDG) structure. Making use of the separate-gated property, it is demonstrated that a proper auxiliary gate bias could enhance programming and erasing efficiency. 2-bit/cell operations can also be realized through two independent ONO storage sites. Such a high-performance poly-Si SONOS device with simple fabrication possesses strong potential for system-on-panel applications and 3D stacked high-density storage devices.