A Tow-Level Buffered SDRAM Controller

Abstract

With the improvement of processor and SDRAM performance, the performance of SDRAM controller becomes the bottleneck of the system performance. In this paper, a Tow-Level Buffered SDRAM controller is proposed, and its design and verification are described. To some extent, the controller improves the throughput of the processor for the SDRAM memory, and provides a solution for the design of high performance system.