Performance of Digital Phase Locked Loop Based on Notch Filter in Industrial ARM-Cortex Microcontrollers

Ade Pratama Suryo Kusumo, E. Firmansyah, F. D. Wijaya
{"title":"Performance of Digital Phase Locked Loop Based on Notch Filter in Industrial ARM-Cortex Microcontrollers","authors":"Ade Pratama Suryo Kusumo, E. Firmansyah, F. D. Wijaya","doi":"10.1109/ICITEED.2019.8929965","DOIUrl":null,"url":null,"abstract":"Phase-locked loop (PLL) is a key algorithm in a grid-connected power converter. The PLL must have excellent performance but consume minimum resources when implemented in a microcontroller.As the phase detector in the PLL system, causing the second harmonic signal, a notch filter is applied to cancel the second and higher harmonic that caused in PLL system to get better output signal. A simple second-order notch filter was implemented on the microcontroller.The performance of implemented digital PLL will be measured through several experiments. The experiment results show that the proposed digital PLL performs well after tested with emulatedvoltage sag, distorted input waveforms, and phase-jump conditions.","PeriodicalId":6598,"journal":{"name":"2019 11th International Conference on Information Technology and Electrical Engineering (ICITEE)","volume":"81 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 11th International Conference on Information Technology and Electrical Engineering (ICITEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICITEED.2019.8929965","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

Phase-locked loop (PLL) is a key algorithm in a grid-connected power converter. The PLL must have excellent performance but consume minimum resources when implemented in a microcontroller.As the phase detector in the PLL system, causing the second harmonic signal, a notch filter is applied to cancel the second and higher harmonic that caused in PLL system to get better output signal. A simple second-order notch filter was implemented on the microcontroller.The performance of implemented digital PLL will be measured through several experiments. The experiment results show that the proposed digital PLL performs well after tested with emulatedvoltage sag, distorted input waveforms, and phase-jump conditions.
基于陷波滤波器的工业ARM-Cortex微控制器数字锁相环性能研究
锁相环算法是并网电源变换器中的关键算法。锁相环必须具有优异的性能,但在微控制器中实现时消耗的资源最少。作为锁相环系统中产生二次谐波信号的鉴相器,陷波滤波器用于消除锁相环系统中产生的二次谐波和更高次谐波,从而得到较好的输出信号。在单片机上实现了一个简单的二阶陷波滤波器。实现的数字锁相环的性能将通过几个实验来测量。实验结果表明,该数字锁相环在仿真电压暂降、畸变输入波形和跳相条件下均具有良好的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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