VLSI layout hotspot detection based on discriminative feature extraction

Abstract

Feature extraction is a key stage in machine learning based VLSI layout hotspot detection flow. Conventional machine learning based methods apply various feature extraction techniques to approximate an original layout structure at nanometer level. However, some important layout pattern information is missed during the approximation process, resulting in performance degradation. In this paper, we present a comprehensive study on layout feature extraction and propose a new method that can preserve discriminative layout pattern information to improve the detection performance in terms of accuracy and extra. Experiments were conducted on an industrial benchmark and ICCAD benchmark suite to study the effectiveness of our proposed methods.