Exploiting parallelism for faster implementation of Bubble sort algorithm using FPGA

Abstract

Sorting is a classic problem that has been studied for decades. From the beginning of computing, many Sorting algorithms have been investigated. Bubble sort is a very common and powerful sorting technique used in different applications. For high speed data processing, we need faster and efficient environment for any sorting algorithm. In this purpose, FPGA based hardware accelerators can show better performance for high speed data processing than the general purpose processors. In this paper, the sequential and parallel bubble sort algorithm is implemented using FPGA. We show that parallel implementation of Bubble sort algorithm is almost 10 times faster than that of sequential implementation for 20 different data inputs. However, this implementation is faster for more data inputs.