Resilient die-stacked DRAM caches

Jaewoong Sim, G. Loh, Vilas Sridharan, Mike O'Connor
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引用次数: 48

Abstract

Die-stacked DRAM can provide large amounts of in-package, high-bandwidth cache storage. For server and high-performance computing markets, however, such DRAM caches must also provide sufficient support for reliability and fault tolerance. While conventional off-chip memory provides ECC support by adding one or more extra chips, this may not be practical in a 3D stack. In this paper, we present a DRAM cache organization that uses error-correcting codes (ECCs), strong checksums (CRCs), and dirty data duplication to detect and correct a wide range of stacked DRAM failures, from traditional bit errors to large-scale row, column, bank, and channel failures. With only a modest performance degradation compared to a DRAM cache with no ECC support, our proposal can correct all single-bit failures, and 99.9993% of all row, column, and bank failures, providing more than a 54,000x improvement in the FIT rate of silent-data corruptions compared to basic SECDED ECC protection.
弹性叠片DRAM缓存
模堆叠DRAM可以提供大量的封装内高带宽缓存存储。然而,对于服务器和高性能计算市场,这种DRAM缓存还必须提供足够的可靠性和容错性支持。虽然传统的片外存储器通过添加一个或多个额外的芯片来提供ECC支持,但这在3D堆栈中可能不实用。在本文中,我们提出了一个DRAM缓存组织,它使用纠错码(ecc),强校验和(crc)和脏数据复制来检测和纠正各种堆叠DRAM故障,从传统的位错误到大规模的行,列,银行和通道故障。与不支持ECC的DRAM缓存相比,我们的建议只有适度的性能下降,可以纠正所有单比特故障,以及99.9993%的行、列和银行故障,与基本的SECDED ECC保护相比,静默数据损坏的FIT率提高了54,000倍以上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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