A low-power single-ended 11-bit SA-ADC with 1 V supply voltage and 2 V input voltage range for CMOS image sensors

Junbo Shim, Min-Kyu Kim, Seongkwan Hong, O. Kwon
{"title":"A low-power single-ended 11-bit SA-ADC with 1 V supply voltage and 2 V input voltage range for CMOS image sensors","authors":"Junbo Shim, Min-Kyu Kim, Seongkwan Hong, O. Kwon","doi":"10.1109/APCCAS.2016.7803989","DOIUrl":null,"url":null,"abstract":"We propose a low-power single-ended 11-bit successive approximation analog-to-digital converter (SA-ADC) for CMOS image sensors. The proposed SA-ADC uses a supply voltage of 1 V instead of 2 V for a 2 V input voltage range in order to reduce power consumption. The proposed ADC reduces the conversion time and area by sampling the input signal only twice and converting it to the most significant bit (MSB) and lower 10-bit without any additional analog circuit. A test chip with the proposed SA-ADC was fabricated using a 0.18 μm CMOS process technology. The measurement results show that the total power consumption of the proposed SA-ADC is 9.0 μW. The static and dynamic power consumptions using a 1 V supply voltage are reduced by 54% and 76%, respectively, compared with those using a 2 V supply voltage. In addition, the proposed SA-ADC achieves a short conversion time of 6.5 μs and occupies a small area of 320 μm × 270 μm. The measured DNL and INL are −0.53/+0.57 LSB and −0.91/+0.71 LSB, respectively.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"135 1","pages":"410-413"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2016.7803989","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

We propose a low-power single-ended 11-bit successive approximation analog-to-digital converter (SA-ADC) for CMOS image sensors. The proposed SA-ADC uses a supply voltage of 1 V instead of 2 V for a 2 V input voltage range in order to reduce power consumption. The proposed ADC reduces the conversion time and area by sampling the input signal only twice and converting it to the most significant bit (MSB) and lower 10-bit without any additional analog circuit. A test chip with the proposed SA-ADC was fabricated using a 0.18 μm CMOS process technology. The measurement results show that the total power consumption of the proposed SA-ADC is 9.0 μW. The static and dynamic power consumptions using a 1 V supply voltage are reduced by 54% and 76%, respectively, compared with those using a 2 V supply voltage. In addition, the proposed SA-ADC achieves a short conversion time of 6.5 μs and occupies a small area of 320 μm × 270 μm. The measured DNL and INL are −0.53/+0.57 LSB and −0.91/+0.71 LSB, respectively.
一款低功耗单端11位SA-ADC,电源电压为1v,输入电压范围为2v,用于CMOS图像传感器
我们提出了一种用于CMOS图像传感器的低功耗单端11位连续近似模数转换器(SA-ADC)。为了降低功耗,建议的SA-ADC在2v的输入电压范围内使用1v的电源电压而不是2v。所提出的ADC通过对输入信号进行两次采样并将其转换为最高有效位(MSB)和更低的10位,而无需任何额外的模拟电路,从而减少了转换时间和面积。采用0.18 μm CMOS工艺制作了SA-ADC测试芯片。测量结果表明,所设计的SA-ADC的总功耗为9.0 μW。与使用2v供电电压相比,使用1v供电电压的静态和动态功耗分别降低54%和76%。此外,SA-ADC的转换时间较短,仅为6.5 μs,占地面积较小,仅为320 μm × 270 μm。测得的DNL和INL分别为- 0.53/+0.57 LSB和- 0.91/+0.71 LSB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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