LEnS: Lifetime Enhancement Coding Scheme for Non-volatile Memory Processors

Abstract

Limited write endurance and high write energy consumption per bit restrict the use of emerging non-volatile memory devices. Many studies concentrate on reducing the number of bit-flips per write operation to reduce bottleneck issues. In this paper, we propose a lifetime enhancement scheme for eNVM device-based memories that distributes the number of bit-flips across the bitstream and can improve the endurance and energy performance of the NVM processors. The proposed scheme significantly reduces the number of bit-flips by ≥40% in write-intensive applications and improves the processor’s performance by ~ 55% as compared to content-aware bit-shuffling scheme.