A Highly Parameterizable Simulator for Performance Analysis of NoC Architectures

Abstract

Network, wireless, and multimedia applications executing on embedded chips demand massive data processing with lesser power consumption today. Journey of a new paradigm in the domain of parallel processing - Network-on-Chip (NoC) starts here. But unlike its simpler look both the design and test costs for this kind of real many-core chips are too high. So efficient and accurate performance estimation tools with respect to the real application ASICs are needed for system level optimization and performance analysis in a cost-effective and flexible way. Simulator that allow exploring the best design options for a system before actually building it has been becoming inevitable in system design and optimization flows. Very few simulators have been developed so far addressing such problems. Some of them are popular with its better accuracy and others with a large set of configurable architectural parameters and traffic options. In this paper, a novel GUI based highly parameterizable NoC simulator has been proposed designed using Qt and System C that is capable of handling real embedded workload traces with custom task allocation support for early exploration of application specific Network-on-Chips.