A linear 0.18um CMOS Distributed Low Noise Amplifier from 3.1 to 10.6 GHz with cascode cells

Abstract

In this paper, we propose a design methodology of 3.1–10.6GHz Ultra-wideband (UWB) Distributed Low Noise Amplifier using standard TSMC 0.18um CMOS technology. The four cells DLNA, each cell contains cascode architecture, can be use in broadband applications. The proposed distributed low noise amplifier has an appropriate input and output matching over the full band of 3.1–10.6 GHz. We achieve acceptable results for low noise amplifier as a flat power gain of 12dB (S21) from 3.1 to 10.6GHz, which is ripple only ±0.3 dB over the full UWB band. The proposed DLNA has an excellent linear behavior. The third intercept point (IIP3) of the proposed DLNA is +2dBm and P1dBin is −12dBm. An input impedance matching is <−15 dB (S11) and an output impedance matching of < −15 dB (S22) over the entire band. This LNA achieves the minimum noise figure of 2.8dB.