A Design Framework for Hardware Approximation of Deep Neural Networks

Abstract

For real-time edge AI applications, there is a need to implement deep neural networks (DNNs) in hardware for high speed. The trade-off between computing accuracy and hardware cost must be made during the implementation of hardware approximation. In this paper, we propose a design framework for DNN hardware approximation. The proposed framework provides a behavior model library of approximate logic circuits (e.g., approximate multipliers) for the designers to utilize them. Moreover, the proposed framework also supports the dynamic fixed-point arithmetic for hardware simulation. To save the required total bit width, we develop an integer length tuning method in the framework to maximize the computing accuracy under a constraint on the total bit width. Experimental results on ICNet show that the proposed framework can achieve high computing accuracy with small hardware cost.