Improvement of bimodal breakdown voltage behavior on thin Oxide POD capacitor

Abstract

Polysilicon-Oxide-Diffusion (POD) capacitor is built on CMOS-based technology by special POD implant below gate oxide. Since the device construction is similar to gate oxide test structure, the standard breakdown voltage measurement is applied to POD as a dielectric integrity qualification. This paper presents an investigation of low oxide breakdown voltage on POD capacitor. The dielectric was 7nm thermal oxide, which was grown simultaneously for MOS transistor as gate oxide. The V-Ramp measurement showed bimodal distribution of Vbd with one circular patch having ≪7V instead of the target Vbd (10V). The size of the patch depends on the POD capacitor area. This behavior was not observed on gate oxide of MOS transistor and 22.5nm POD capacitor. Process partition check, including wafer orientation and wafer slot arrangement was conducted. The patch signature has been identified closely related to the cleaning step before POD gate oxidation. Further process improvement on resist removal has successfully eliminated the patch signature giving much more process margin for subsequent cleaning steps.