Energy-efficient hybrid adder design by using inexact lower bits adder

Abstract

Approximation in the adder logic is a promising solution for energy-efficient designs in various applications. In this study, new hybrid adder design, which consists of an accurate adder for higher bits and proposed approximate adders for lower bits, is investigated. The XOR-based inexact adder is modified to be used in the approximation part. Simulation results of 16-bits adders show that error rates can be reduced significantly by the proposed hybrid adder compared to other approximation adders with smaller number of transistors than an accurate adder.