Facet Suppression in (100) GaAs spalling via use of a Nanoimprint Lithography Release Layer

Abstract

Controlled spalling is an emerging technique developed for fast, scalable wafer reuse, but for the commonly used (100) GaAs substrate system, the process leaves large facets ranging from 5-10 µm on the wafer surface. Removing them for wafer reuse requires a costly re-polishing step that limits the cost savings that can be achieved with spalling as a wafer reuse technique. In this study, we investigate facet suppression in spalling of (100) GaAs by redirecting the fracture front along features created by buried nanoimprint lithography (NIL)-patterned SiO2. We show successful facet suppression using patterns that result in favorable fracture along the SiO2/GaAs interface. The results from this work show NIL patterned interlayers are a promising method for faceting suppression in (100) GaAs spalling.