An Automatic VHDL Testbench Generator for Medium Complexity Design

Abstract

Design verification is one of the most time-consuming and labor-intensive process in semi-conductor industry. With every growing complexity of electronics designs, verification process become more time consuming so is the time needed to market the product. Furthermore, commercially available automatic testbench tools are either too costly or not being open source particularly for academic purpose. Hence, automatic testbench generator has been developed with intention to reduce the amount time and effort to generate testbench. This paper presents a method of developing automatic testbench tool that is able to develop VHDL testbenches for asynchronous, synchronous, and finite state machine VHDL design files by incorporating the user input parameters. Furthermore, with addition of GUI, the tool is simple and user friendly that develops VHDL testbench rapidly. The tool also incorporates the testbench coverage feature to indicate effectiveness of the developed testbench by indicating the activity of the design nodes, number of times the nodes are tested and percentage of the code coverage. The tool is tested on a few medium complexity designs and the results shows that the developed testbenches provide more than 90% code coverage.