Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs

Abstract

Symbol-based and linear-based test-data compression techniques have complementary properties which are very attractive for testing multi-core SoCs. However, only linear-based techniques have been adopted by industry as the symbol-based techniques have not yet revealed their real potential for testing large circuits. We present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques under a unified solution for multi-core SoCs. The proposed method offers higher compression than any other method presented so far, very low shift switching activity and very short test sequence length at the same time. Moreover, contrary to existing techniques, it offers a complete solution for testing multi-core SoCs as it is suitable for cores of both known and unknown structure (IP cores) that usually co-exist in modern SoCs. Finally, it supports very low pin-count interface as it needs only one tester channel to download fast the compressed test data on-chip.