A 20b clockless DAC with sub-ppm-linearity 7.5nV/vHz-noise and 0.05ppm/°C-stability

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Pub Date : 2013-03-28 DOI:10.1109/ISSCC.2013.6487734

R. McLachlan, A. Gillespie, M. Coln, Douglas Chisholm, Denise T. Lee

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引用次数: 3

Abstract

DACs without continuous clocking are often favored in applications such as medical imaging and scientific instrumentation. The DACs in these high-precision systems are commonly endpoint-calibrated. After this calibration, a non-ideal DAC contributes three main sources of error: noise, temperature drift, and INL. The segmented voltage-mode R-2R DAC is an attractive architecture for reducing the first two of these error sources. Resistor Johnson noise is fixed by the DAC's code-independent output resistance, which is readily lowered by the combination of several parallel segments. The complete signal path can be built using opamps that have a minimal noise gain of unity. This architecture also benefits from inherently zero endpoint error, avoiding any gain or offset drift over temperature. However, this preferred architecture for noise and temperature drift suffers from several sources of INL including: resistor mismatch, voltage losses across CMOS switches, and the nonlinearity of each resistor.

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20b无时钟DAC，亚ppm线性度，7.5nV/ vhz噪声，0.05ppm/°c稳定性

没有连续时钟的dac通常在医学成像和科学仪器等应用中受到青睐。这些高精度系统中的dac通常是端点校准的。在此校准之后，非理想DAC有三个主要误差来源:噪声、温度漂移和INL。分段电压模式R-2R DAC是减少前两个误差源的有吸引力的架构。电阻器约翰逊噪声由DAC的代码无关输出电阻固定，通过几个并联段的组合可以很容易地降低输出电阻。完整的信号路径可以使用噪声增益为单位的最小运放大器来构建。该架构还受益于固有的零端点误差，避免了任何增益或偏置漂移。然而，这种用于噪声和温度漂移的首选架构受到几个INL来源的影响，包括:电阻失配，CMOS开关的电压损失以及每个电阻的非线性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

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