A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC

Abstract

DACs based on switched-capacitor feedback are used in CTΔΣMs to achieve low jitter sensitivity. Unfortunately, they all severely compromise the alias rejection of the modulator around multiples of the sampling frequency. We introduce the Dual Switched-Capacitor Return-to-Zero (Dual-SCRZ) DAC, which addresses this problem. It combines the low clock jitter sensitivity of a Switched-Capacitor DAC with the low peak-to-average ratio characteristic of an NRZ DAC. A single-bit continuous-time ΔΣ modulator that uses the Dual-SCRZ technique and opamp-assistance to improve linearity and reduce jitter sensitivity achieves 91/85.1/83dB DR/SNR/SNDR in a 2MHz bandwidth. Operating at a sampling rate of 256MHz in a 0.18μm CMOS process, the CTDSM dissipates 14.8mW from a 1.8V supply.