VHDL-based behavioural description of pipeline ADCs

Abstract

This paper proposes a behavioural model for digitally corrected/calibrated pipeline A/D converters (ADCs) based on standard VHDL. We will show how VHDL-based analog modelling can be efficiently used to simulate and verify the functionality of these mixed-signal systems where significant interaction exists between analog and digital parts. The main motivation for describing the behavioural model (analog and digital) directly in standard VHDL is to make possible the synthesis and fault simulation of the digital part using standard digital tools. Results from simulations carried out using QuickHDL in Mentor-Graphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a Silicon prototype.