Retention Enhancement through Architecture Optimization in Junctionless Capacitorless DRAM

Md. Hasan Raza Ansari, A. Kranti
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Abstract

The work shows the significance of device architecture to enhance the Retention Time (RT) of Junctionless Capacitorless Dynamic Random Access Memory (1T-DRAM). The conduction and storage regions of the DRAM are segregated through an oxide. The top (n-type) region is utilized for conduction while back region (p-type) for charge storage. A potential well, required to store charges, is also achieved through a Metal-Oxide-Semiconductor (MOS) effect. A maximum RT of $\sim 3.8\mathrm{s}$ is achieved with gate length of 200 nm and is scaled down to 10 nm with RT of $\sim 1$ ms at $85^{\circ}\mathrm{C}$. The significance of scaling down total length and thickness is examined. It is possible to scale the bias required to perform Write “1” operation (generation of holes) through Band-to-Band-Tunneling (BTBT) to 0.5 V for gate length of 25 nm with RT of $\sim 220$ ms at $85^{\circ}\mathrm{C}$.
无结无电容DRAM的架构优化提高保留率
研究结果表明,器件结构对提高无接点无电容动态随机存取存储器(1T-DRAM)的保持时间(RT)具有重要意义。DRAM的传导区和存储区通过氧化物分离。顶部(n型)区域用于传导,背面(p型)区域用于电荷存储。存储电荷所需的电位阱也可以通过金属氧化物半导体(MOS)效应实现。当栅极长度为200 nm时,最大RT为$\sim 3.8\mathrm{s}$;当栅极长度为$85^{\circ}\mathrm{C}$时,最大RT为$\sim 1$ ms,最大RT降至$ 10 nm。研究了缩小总长度和总厚度的意义。通过带对带隧道(BTBT)进行写“1”操作(产生空穴)所需的偏置可以缩放到0.5 V,栅极长度为25 nm, RT为$ $ sim 220$ ms,温度为$85^{\circ}\ mathm {C}$。
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