Design analysis of metallic single electron tunneling circuits

Abstract

We carried out a design study of single electron devices based on submicron metallic islands and tunnel junctions. The results of a first capacitive design analysis using a three-dimensional numerical field computation of separated circuit cells are used as input for an optimization with respect to cross-talk between neighboring circuit cells. We discuss the reduction of parasitic effects by use of additional shielding electrodes on the top of the substrate or in the background. In view of the influenced charge associated with parasitic background charges we discuss the charge distribution on a three-dimensional scan of the substrate below the structures for the study of critical influence regions, where a certain threshold of influenced charge at neighbor electrodes is given. We show that the influence calculation of the parasitic background charge is of significant importance for the design and fabrication of single charge circuits.