Optimization of multiplexer architecture in VLSI circuits

Abstract

In this paper, we develop n variable logic function using Multiplexer which is used to implement (n-1) variable Multiplexer. This reduces the architecture for implementation of any logic in gate level and thereby makes the hardware of the circuit less complex. This method also effects on area, power, delay which makes the system more efficient and reliable. Initially the three variable logic functions are implemented using 8x1 Multiplexer and then after the same logic is implemented using 4x1 Multiplexer. By this method of implementation, power is decreased by 10%, I/O Blocks are reduced by 20% and dynamic power consumption is reduced by 4% reduced which were shown in results. In our paper, the various parameters are compared and analyzed using Vivado tool.