{"title":"A digital dither controlled step-up/step-down DC-DC converter with smooth transition","authors":"Yanzhao Ma, Hongyi Wang, Guican Chen","doi":"10.1109/EDSSC.2011.6117631","DOIUrl":null,"url":null,"abstract":"A step-up/step-down DC-DC converter with high efficiency and small output voltage ripple is proposed in this paper. To reduce the switching loss and improve the efficiency, the converter operates in buck or boost mode when the input voltage is much higher or lower than the output voltage. However, a large output voltage ripple appears at the boundary of buck mode and boost mode due to the speed limitation of standard analog circuit. A transition mode using a digital dither technique is adopted and the output voltage ripple is reduced when the input voltage is close to the output voltage. Furthermore, the average inductor current is also reduced in the proposed transition mode. The converter has been designed with a standard a 0.5 µm CMOS process. The peak efficiency is 96% and the output voltage ripple is reduced to less than 10 mV in the transition mode.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2011.6117631","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A step-up/step-down DC-DC converter with high efficiency and small output voltage ripple is proposed in this paper. To reduce the switching loss and improve the efficiency, the converter operates in buck or boost mode when the input voltage is much higher or lower than the output voltage. However, a large output voltage ripple appears at the boundary of buck mode and boost mode due to the speed limitation of standard analog circuit. A transition mode using a digital dither technique is adopted and the output voltage ripple is reduced when the input voltage is close to the output voltage. Furthermore, the average inductor current is also reduced in the proposed transition mode. The converter has been designed with a standard a 0.5 µm CMOS process. The peak efficiency is 96% and the output voltage ripple is reduced to less than 10 mV in the transition mode.