A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS

Abstract

1Mbit SRAM macro with adaptive leakage current reduction scheme is implemented in 28nm high-k metal gate CMOS technology. A current limiter that limits cell array leakage current at various process-voltage-temperature (PVT) corners is included in the proposed scheme. The leakage current is reduced by more than 60% at fast process corners by increasing virtual ground voltage (Vvgnd) while maintaining sufficient data retention margin. At low VDD or slow process corners, Vvgnd is lowered to maintain the data integrity in the bitcell.