Impact of size variation in junctionless vs junction planar SOI n-MOSFET transistor

Abstract

In this paper, the effect of silicon body thickness (TSi) and silicon body width (WSi) variation on DC characteristics in 100 nm gate length silicon-on-insulator (SOI) junctionless (JL) and junction transistors has been investigated by using numerical simulations. The digital figure-of-merits characteristics such as threshold voltage (VTH), on-current, subthreshold voltage, and drain-induced-barrier-lowering are the main parameters that have been investigated. Based on the simulations, the JT device is less sensitive to variation of TSi and WSi compared to JLT.