A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573523

Yuan Du, Wei-Han Cho, Yilei Li, C. Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, S. Lee, Mau-Chung Frank Chang

{"title":"A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS","authors":"Yuan Du, Wei-Han Cho, Yilei Li, C. Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, S. Lee, Mau-Chung Frank Chang","doi":"10.1109/VLSIC.2016.7573523","DOIUrl":null,"url":null,"abstract":"A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 μW/Gb/s/dB considering channel condition.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"26 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573523","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 12

Abstract

A cognitive tri-band transmitter with forwarded clock using multi-band signaling and high-level digital signal modulations is presented for serial link application. The transmitter features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level, and accordingly adapts modulation scheme, data bandwidth and carrier frequency. The modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The highly re-configurable transmitter is capable of dealing with low-cost serial link cables/connectors or multi-drop buses with deep and narrow notches in frequency domain (e.g. 40dB loss at notches). The adaptive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented transmitter consumes 14.7mW power and occupies 0.016mm2 in 28nm CMOS. It achieves a maximum data rate of 16Gb/s per differential pair and the most energy-efficient FoM (defined in Fig. 8) of 20.4 μW/Gb/s/dB considering channel condition.

查看原文本刊更多论文

16Gb/s 14.7mW三频带认知串行链路发送器，时钟转发，支持PAM-16 / 256-QAM和28 nm CMOS通道响应检测

提出了一种基于多频带信令和高级数字信号调制的时钟转发认知三频带发射机，用于串行链路应用。发射机的特点是通过发送连续波的扫描来学习任意信道响应，检测功率电平，并相应地适应调制方案、数据带宽和载波频率。调制方案从NRZ/QPSK到PAM-16/256-QAM。高度可重新配置的发射器能够处理低成本的串行链路电缆/连接器或多滴总线，在频域具有深而窄的陷波(例如陷波损耗为40dB)。自适应多频带方案通过避免频率陷波，利用最大可用信噪比和信道带宽，降低了均衡性要求，提高了能量效率。所实现的发射器功耗为14.7mW，在28nm CMOS中占地0.016mm2。每个差分对的最大数据速率为16Gb/s，考虑信道条件，最节能的FoM(定义见图8)为20.4 μW/Gb/s/dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

自引率

0.00%

发文量