J. Lai, Chi-Hsueh Wang, Kaipon Kao, A. Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Y. Chung, Paul C. P. Liang, G. Dehng, Hung-Sung Li, G. Chien, R. Staszewski
{"title":"A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS","authors":"J. Lai, Chi-Hsueh Wang, Kaipon Kao, A. Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Y. Chung, Paul C. P. Liang, G. Dehng, Hung-Sung Li, G. Chien, R. Staszewski","doi":"10.1109/ISSCC.2013.6487762","DOIUrl":null,"url":null,"abstract":"An all-digital polar transmit (TX) architecture exhibits advantages of low cost, low power, as well as reconfigurability with full usage of digital computational power. The design challenge is the need for continuous innovation to further enhance power efficiency and minimize silicon area while achieving the best-in-class RF performance. The design must also meet the increasing demand of concurrent operation for multi-radio SoC integration. The presented Bluetooth TX demonstrates advancements in this direction with over 30% power and 66% area reduction.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":"54 1","pages":"342-343"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2013.6487762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 23
Abstract
An all-digital polar transmit (TX) architecture exhibits advantages of low cost, low power, as well as reconfigurability with full usage of digital computational power. The design challenge is the need for continuous innovation to further enhance power efficiency and minimize silicon area while achieving the best-in-class RF performance. The design must also meet the increasing demand of concurrent operation for multi-radio SoC integration. The presented Bluetooth TX demonstrates advancements in this direction with over 30% power and 66% area reduction.