Synthetic Laboratory Imitation of Transient Voltage Stresses of MMC-HVDC Links

2018 IEEE International Conference on Environment and Electrical Engineering and 2018 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I&CPS Europe) Pub Date : 2018-06-01 DOI:10.1109/EEEIC.2018.8494381

Claudius Freye, Jens Kortenbrede, Lars Vogelsang, F. Jenau

{"title":"Synthetic Laboratory Imitation of Transient Voltage Stresses of MMC-HVDC Links","authors":"Claudius Freye, Jens Kortenbrede, Lars Vogelsang, F. Jenau","doi":"10.1109/EEEIC.2018.8494381","DOIUrl":null,"url":null,"abstract":"Overvoltages occuring in High Voltage Direct Current (HVDC) links during pole to ground faults of Modular Multilevel Converters (MMC-HVDC) differ significantly from the normative switching impulse (SI) or normatively predefined slow front overvoltage waveforms. Knowledge on insulation system behaviour under consideration of those non-standard impulses is rare. However, for insulation coordination strategies of MMC-HVDC, this information gains in importance in order to determine insulation worst case stresses. For this purpose, a suitable and scalable laboratory test setup for the imitation of expected MMC-HVDC transient stresses is presented. Besides the presentation of a theoretically modelling approach and basic circuit design rules, a small scale laboratory realization is presented and obtained results are discussed. This setup is scalable and suitable for future investigations on related dielectric effects caused by those non-normative impulses.","PeriodicalId":6563,"journal":{"name":"2018 IEEE International Conference on Environment and Electrical Engineering and 2018 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I&CPS Europe)","volume":"2 1","pages":"1-6"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Environment and Electrical Engineering and 2018 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I&CPS Europe)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EEEIC.2018.8494381","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

Abstract

Overvoltages occuring in High Voltage Direct Current (HVDC) links during pole to ground faults of Modular Multilevel Converters (MMC-HVDC) differ significantly from the normative switching impulse (SI) or normatively predefined slow front overvoltage waveforms. Knowledge on insulation system behaviour under consideration of those non-standard impulses is rare. However, for insulation coordination strategies of MMC-HVDC, this information gains in importance in order to determine insulation worst case stresses. For this purpose, a suitable and scalable laboratory test setup for the imitation of expected MMC-HVDC transient stresses is presented. Besides the presentation of a theoretically modelling approach and basic circuit design rules, a small scale laboratory realization is presented and obtained results are discussed. This setup is scalable and suitable for future investigations on related dielectric effects caused by those non-normative impulses.

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MMC-HVDC线路瞬态电压应力的综合实验室模拟

模块化多电平变换器(MMC-HVDC)在极地故障时发生在高压直流(HVDC)链路中的过电压与规范的开关脉冲(SI)或规范预定义的慢前过电压波形有很大不同。关于考虑这些非标准脉冲的绝缘系统行为的知识很少。然而，对于MMC-HVDC的绝缘协调策略，这些信息对于确定绝缘最坏情况应力变得非常重要。为此，提出了一种适合的、可扩展的实验室测试装置，用于模拟MMC-HVDC的瞬态应力。除了给出理论建模方法和基本电路设计规则外，还给出了一个小规模的实验室实现，并讨论了得到的结果。该装置具有可扩展性，适用于未来对非规范脉冲引起的相关介电效应的研究。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2018 IEEE International Conference on Environment and Electrical Engineering and 2018 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I&CPS Europe)

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